Presentation / Installation
Senior System IP Design Verification Engineer – Coherent Interconnect
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Samsung Austin R&D Center - Advanced Computing Lab
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Austin, San Jose, San Diego
SessionJob Postings
DescriptionPosition Summary
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role and Responsibilities
As a Sr. System IP Design Verification Engineer, you will work as part of a custom System IP team to drive the functional verification of coherent interconnect, system caching and dynamic memory controllers. This is an individual contributor role with the potential for leadership for well qualified candidates. You will be tasked with formulating, driving and executing the Design Verification plan to ensure the high quality of various sub-blocks of the coherent interconnect and the memory controller IP. Solid background in Design Verification is desired for success.
Key responsibilities include:
- Work with architects and designers to build verification environments and test plans.
- Craft functional verification coverage strategy to ensure complete test suite implementation.
- Develop assertions and checks to optimize isolation time and produce meaningful failing signatures.
- Analyze failing tests to root cause along, working with RTL and reference modeling teams.
- Provide input on Architectural and Micro-Architectural specifications for testability and accuracy.
- Examine code coverage results, identifying exclusions and improving stimulus.
- Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics.
- Work with RTL to create verification reference models and constrained random stimulus generators.
- Lead and mentor junior team members.
- Own test bench, manage tasks and deliverables to meet milestones.
- Maintain Verification IPs for various bus interfaces.
Skills and Qualifications
Minimum requirements:
- MS Computer Engineering, MSEE, or comparable and 10+ years industry experience in a design verification role
- Must have professional experience with Coherent Interconnect, MESI/MOESI protocols
- Must have experience working with Coherency Managers, L3/System-Level Cache, Snoop Filters
- Professional experience with LPDDR Memory Controller verification
- Experience building UVM Test Benches from scratch.
- Experience working with Coherency Protocols
- Experience working with ARM protocols – AXI, ACE, CHI, APB
- Proficient in System Verilog/UVM, Verdi, and OOP/C++
- Deep understanding of constrained randomization and the development of efficient test suites
- Experience with code coverage and functional coverage driven verification methodology
- Excellent communication skills and be able to work with cross-functional teams to execute verification plan
- Proficient RTL skills – can read and understand RTL to create/execute verification plans
Preferred Qualifications:
- Energetic, curiosity, and passion in design verification
- Good written and verbal communication skills
- Knowledge of coherent interconnect and bus protocols – AMBA interconnect experience preferred
- Knowledge of memory subsystem design including cache subsystem design
Compensation for this role will vary among specific regions due to geographic differentials in the labor market, actual pay will be determined considering factors such as relevant skills and experience, and comparisons to other employees in the role. However, compensation in the following regions is expected to be as follows:
Colorado: Compensation is expected to be between $174,557 to $270,563
NYC: Compensation is expected to be between $174,557 to $270,563
Washington State: Compensation is expected to be between $197,041 to $305,414
California: Compensation is expected to be between $197,041 to $305,414
Regular full-time employees (salaried or hourly) have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
*This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export controlled information or be eligible to receive a government authorization to access export-controlled information
* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role and Responsibilities
As a Sr. System IP Design Verification Engineer, you will work as part of a custom System IP team to drive the functional verification of coherent interconnect, system caching and dynamic memory controllers. This is an individual contributor role with the potential for leadership for well qualified candidates. You will be tasked with formulating, driving and executing the Design Verification plan to ensure the high quality of various sub-blocks of the coherent interconnect and the memory controller IP. Solid background in Design Verification is desired for success.
Key responsibilities include:
- Work with architects and designers to build verification environments and test plans.
- Craft functional verification coverage strategy to ensure complete test suite implementation.
- Develop assertions and checks to optimize isolation time and produce meaningful failing signatures.
- Analyze failing tests to root cause along, working with RTL and reference modeling teams.
- Provide input on Architectural and Micro-Architectural specifications for testability and accuracy.
- Examine code coverage results, identifying exclusions and improving stimulus.
- Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics.
- Work with RTL to create verification reference models and constrained random stimulus generators.
- Lead and mentor junior team members.
- Own test bench, manage tasks and deliverables to meet milestones.
- Maintain Verification IPs for various bus interfaces.
Skills and Qualifications
Minimum requirements:
- MS Computer Engineering, MSEE, or comparable and 10+ years industry experience in a design verification role
- Must have professional experience with Coherent Interconnect, MESI/MOESI protocols
- Must have experience working with Coherency Managers, L3/System-Level Cache, Snoop Filters
- Professional experience with LPDDR Memory Controller verification
- Experience building UVM Test Benches from scratch.
- Experience working with Coherency Protocols
- Experience working with ARM protocols – AXI, ACE, CHI, APB
- Proficient in System Verilog/UVM, Verdi, and OOP/C++
- Deep understanding of constrained randomization and the development of efficient test suites
- Experience with code coverage and functional coverage driven verification methodology
- Excellent communication skills and be able to work with cross-functional teams to execute verification plan
- Proficient RTL skills – can read and understand RTL to create/execute verification plans
Preferred Qualifications:
- Energetic, curiosity, and passion in design verification
- Good written and verbal communication skills
- Knowledge of coherent interconnect and bus protocols – AMBA interconnect experience preferred
- Knowledge of memory subsystem design including cache subsystem design
Compensation for this role will vary among specific regions due to geographic differentials in the labor market, actual pay will be determined considering factors such as relevant skills and experience, and comparisons to other employees in the role. However, compensation in the following regions is expected to be as follows:
Colorado: Compensation is expected to be between $174,557 to $270,563
NYC: Compensation is expected to be between $174,557 to $270,563
Washington State: Compensation is expected to be between $197,041 to $305,414
California: Compensation is expected to be between $197,041 to $305,414
Regular full-time employees (salaried or hourly) have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
*This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export controlled information or be eligible to receive a government authorization to access export-controlled information
* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
katerina.le@partner.samsung.com
2023-06-30
Event Type
Job Posting
TimeSunday, 6 August 20238am - 9:30am PDT
Location
Session TimeSunday, 6 August 20238am - 9:30am PDT
Location
